SystemC synthesis subset standard ..

Over the past two years, a small group of Verilog-AMS and SystemVerilog experts have been meeting with the goal of unifying SystemVerilog and Verilog-AMS. This tutorial will provide an introduction to the concepts underlying the upcoming SystemVerilog-AMS language standard.

from the OSCI TLM-2.0 Standard and Synthesis Subset Tutorial ..

others from the OSCI TLM-2.0 Standard and Synthesis Subset Tutorial ..
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An introduction to the SystemC synthesis subset standard:

We in the Accellera SystemC Synthesis Working Group (SSWG) think the answer is YES. The most recent draft of a synthesizable subset standard for SystemC has been available for public review and we’d like to introduce it to you. This tutorial is focused on the engineer today who is coding in Verilog/SystemVerilog or VHDL. We will explain how to use the language subset to write synthesizable models at a higher level of abstraction than RTL. We will provide real code examples comparing algorithms written at RTL and those written using the synthesizable subset, explaining the reasons behind the coding choices and the downstream implications for RTL and gates. We will also discuss how a synthesis standard is the foundation for a full design and verification ecosystem at a higher level of abstraction and the value that can bring to the designer.

Video Tutorials and Presentations - Accellera

Implemented as synthesizable intellectual property (IP), the new Ice-Grain subsystem will work with any interconnect and can bring sophisticated energy-saving technology to any SoC design.

Read More → "OSCI Introduces SystemC Synthesis Subset Draft Standard ..
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