Mentor Graphics Catapult C adds SystemC synthesis, …

Divyaraj Desai is a Member of the Research Staff in the Energy Systems and Materials group at PARC. His areas of expertise include electrochemical systems for energy storage, electrochemical sensors, solid-state ion transport, desalination and high-temperature systems. At PARC, Divyaraj has contributed to the development of an intermediate-temperature hydrocarbon fuel cell to directly produce electricity from natural gas, an ambient pressure electrochemical seawater desalination system, an intermediate-temperature ammonia synthesis process. Recently, his idea for a CO2 removal system for improving building efficiency and occupant health was selected by the California Clean Energy fund (CALCEF) for a seedling award.

the Catapult C Synthesis tool ..

C- B a s e d D e s i g n Catapult C Synthesis D A T A ..

interfaces with Interface Synthesis technology ..

Catapult C enables us to quickly specify the ports on the design (RAM, register, FIFO, etc) using interface synthesis. The loop hierarchy of the design is presented graphically in the tool, allowing us to partially or fully unroll loops, as well as to control loop pipelining and resource sharing globally or at the component level.

Using the Mentor Catapult C Synthesis tool, ..

In the TLMs of the encoders, the behavior of the Pixelpipe, DCT, Quantize and Huffmanize blocks is implemented by calling procedures that execute sequential C code provided by Mentor Graphics. This C code operates on algorithmic C bit-accurate data types. These allow you to anticipate the replacement of the reference model with the cycle- and bit-accurate model obtained after the hardware undergoes high-level synthesis with Mentor’s Catapult C software.

01/06/2004 · Catapult C presents an interface that is easily ..
Interface Synthesis refers to the ability to accept pure C/C++ description as its input, ..

Catapult C is a High-Level Synthesis ..

To validate the quality of the results produced by algorithmic C synthesis, we decided to use Mentor Graphics’ Catapult C toolset to automatically generate RTL for an existing design that was already in prototype evaluation. All of the C++ models and most of the RTL code for the initial version had been manually created using the team’s traditional design flow. As the RTL code had already been created, the design would provide an ideal comparison for our evaluation of C-based synthesis. Specifically, the evaluation design was made up of five FPGAs used to implement the functionality of the eventual single ASIC.

Catapult™ C Synthesis Crossing the Gap between Algorithm and Hardware Architecture

Timing analysis (STA) & optimization, Interface Synthesis, ..

High-level synthesis typically also includes a bit-accurate executable specification as input, since to derive an efficient hardware implementation, additional information is needed on what is an acceptable Mean-Square Error or Bit-Error Rate etc. For example, if the designer starts with an FIR filter written using the "double" floating type, before he or she can derive an efficient hardware implementation, they need to perform numerical refinement to arrive at a fixed-point implementation. The refinement requires additional information on the level of quantization noise that can be tolerated, the valid input ranges etc. This bit-accurate specification makes the high level synthesis source specification functionally complete. Normally the tools infer from the high level code a Finite State Machine and a Datapath that implement arithmetic operations.

Mentor also introduced interface synthesis to map the data transfer ..

that Catapult C Synthesis tool allowed us to ..

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